As processor clock speeds increase and power consumption budgets decrease, processor and computer system designers must develop new ways to control power without degrading performance. Power and performance considerations become increasingly significant as the number of processors within a microprocessor die or the number of processors on separate die within the same computer system increases.
Typically, microprocessor and computer system designers must work within a voltage/frequency (“V/f”) envelope when designing the processor system. For example, a processor having multiple processor cores may be capable of operating each core at a maximum frequency at certain operating voltage levels. However, the processor or system may have to be designed such that the processors do not operate at their maximum frequency across all possible operating voltages for extended periods of time, because doing so may result in damage to one or more of the processors or the computer system.
Dynamic power consumption of a processor or computer system can be calculated using various equations or algorithms, including: P=A*C*V2*f, where “P” is power, “A” is activity of the processor or system, “C” is the capacitance observed by the processor or system, “V” is the operating voltage, and “f” is the frequency of the processor(s). Prior art techniques for preventing a processor or system from exceeding the maximum sustainable voltage and frequency include analog detection mechanisms that sense when a processor or system is becoming too hot or consuming too much current. The detection mechanism may then force the voltage and/or frequency lower in response to detecting that the processor or system has exceeded thermal or current consumption limits.
Analog detection mechanisms, however, are limiting in the sense that processor or system performance is not determinable and may depend upon the manufacturing characteristics of the processor or system, operating environment, and other factors. Furthermore, analog detection mechanisms may require that the voltage and frequency of the processor or system be set at conservative levels to ensure enough time to react to sudden variations in current drawing or thermal events. These variations can be caused by changes in activity level on the processor or system due to program execution characteristics. For example the processor might be mostly idle, waiting for data to return from main memory one moment, and in the next moment, when the data has returned, it may be executing instructions at peak rate.
Prior art power control techniques include micro-architectural regulating techniques, such as controlling the number of instructions issued within a processor per processor cycle. Typically, instruction issue rate control techniques prevent the processor from issuing instructions for execution per cycle above a certain threshold. The maximum instruction rate is typically set once for a relatively long interval on the processor, (i.e. the instruction rate control threshold cannot be changed numerous times in short succession during the normal operation of the processor (“dynamically”), but must be changed, if at all, by firmware or software writing a configuration register at longer range intervals.
As with analog detection mechanisms, typical instruction rate control techniques require a conservative approach in order to prevent the processor from being harmed in the event of a sudden variation in current, performance, or thermal characteristics of the processor. In the case of prior art instruction rate control techniques, this means that a sudden increase in performance demand cannot be handled by the processor, thereby incurring performance penalties.